This invention generally relates to the art of electrical connections and, particularly, to a contactless interconnecting system between a computer chip package and a circuit board.
As semiconductor devices become more complex, the interconnections between the silicon wafer or xe2x80x9cdiexe2x80x9d and appropriate circuit hardware continue to evolve and become more complex because of the difficulty of mechanical interconnections. This is due, in part, to the ever-increasing miniaturization and high density of electronic circuitry. Transmitted signals are becoming faster and faster (i.e., higher frequencies) and semiconductor packages are becoming thinner and thinner (i.e., closely compacted). In some anticipated applications, it may be practically impossible to use conventional interconnecting systems, i.e., typical metal contacts or terminals.
Typical mechanical interconnecting systems incorporate conventional terminal pins and sockets or other male and female configurations or interengaging spring connections. With such traditional metal-to-metal interconnections, it is essential to provide a wiping action between the terminals or contacts to remove contaminants or oxidants. Unfortunately, miniaturized semi-conductor interconnections are so small that such traditional mechanical interconnecting systems are not possible. Even traditional solder connections are difficult if at all possible because of the extremely complex hard tooling required for use with miniaturized or closely spaced components of a semi-conductor interconnecting system. In some applications, it may be necessary to rely on electrical or magnetic field coupling as a possible alternative, and the present invention is directed to satisfying this need and solving the problems enumerated above.
An object, therefore, of the invention is to provide a new and improved contactless interconnecting system, particularly such a system between a computer chip package and a circuit board.
In the exemplary embodiment of the invention, a computer chip package includes a substantially planar lower surface having a pattern of discrete terminal lands. A circuit board has a substantially planar upper surface spaced from and generally parallel to the lower surface of the chip package. The upper surface of the circuit board has a pattern of discrete circuit pads aligned with the terminal lands on the lower surface of the computer chip package. A plurality of discrete interposer members are provided between the terminal lands and the circuit pads. The interposer members are in a pattern corresponding to and aligned with the aligned pattern of terminal lands and circuit pads. The interposer members are of a material having a relatively high dielectric constant.
As disclosed herein, the terminal lands are on a lower surface of a wall of the computer chip package. The terminal lands are connected by vias through the wall to leads from a silicon wafer of the package.
In one embodiment of the invention, the interposer members are adhered either to the terminal lands or to the circuit pads. In another embodiment of the invention, the interposer members are supported by a planar carrier disposed between the lower surface of the chip package and the upper surface of the circuit board. The planar carrier may be fabricated of dielectric elastomeric material, and the interposer members may be overmolded in the planar carrier member.
Other objects, features and advantages of the invention will be apparent from the following detailed description taken in connection with the accompanying drawings.